Sleep state transitioning

ABSTRACT

A system has a processor with multiple states, including an awake state and a sleep state, a memory subsystem including a memory controller and memory devices, and a second memory. The system uses software in the second memory to initialize the memory controller upon a transition from a sleep state to an awake state. The system detects a wake event trigger, and in response to the wake event trigger, executes software stored in the second memory to initialize the memory controller, and then executes software out of the first memory after the initialization.

FIELD OF THE INVENTION

[0001] This invention relates to sleep state transitioning.

BACKGROUND

[0002] To implement low power “sleep” states in processor systems,INTEL(TM) and others have proposed the Advanced Configuration and PowerInterface Specification (“ACPI”). ACPI defines an interface between theoperating system and hardware that allows operating systems and hardwareto interact, while permitting the design of operating systems andhardware to evolve independently. The description of the S1 and S2 sleepstates found in the ACPI Specification, Revision 1.0b, released Feb. 2,1999 is reproduced in an Appendix to this specification.

[0003] RAM subsystems can also have low power states. In some RAMsubsystems, a memory controller communicates with the memory chips usinga particular protocol. The memory controller is an intelligent devicethat is initialized before it begins the normal operation of readingdata from and writing data to the memory chips. In the RDRAM(™) RAMsubsystem, developed by RAMBUS(™), Inc. of Mountainview Calif., thememory controller includes a RAMBUS ASIC Cell (“RAC”) that controls theelectrical interface to the memory chips, performs multiplexing anddemultiplexing functions, and converts data between a high speedproprietary serialized interface to the memory chips and the lower speedparallel interface used by the processor. The RDRAM subsystem can bepowered down to conserve power. The RDRAM subsystem must bereinitialized after being powered down.

SUMMARY OF THE INVENTION

[0004] A system has a processor with multiple states, including an awakestate and a sleep state, a memory subsystem including a memorycontroller and memory devices, and a second memory. The system usessoftware in the second memory to initialize the memory controller upon atransition from a sleep state to an awake state. The system detects awake event trigger, and in response to the wake event trigger, executessoftware stored in the second memory to initialize the memorycontroller, and then executes software out of the first memory after theinitialization.

[0005] In another aspect of the invention, the memory subsystem is RAMbased and stores some or all of the operating system software. Thesoftware that initializes the memory controller is stored in the BIOSstorage device. Prior to transitioning from an awake state to a sleepstate, the operating system controls the preparation for the transition.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006]FIG. 1 is a block diagram of a processor system incorporating theinvention.

[0007]FIG. 2 is a flow chart depicting a set of state transitionsperformed by the system of FIG. 1.

[0008]FIG. 3 is a flow chart depicting a transition to and from the S1state performed by the system of FIG. 1.

[0009]FIG. 4 is a flow chart depicting a transition to and from the S2state performed by the system of FIG. 1.

[0010]FIG. 5 is a block diagram illustrating another processor system.

[0011]FIG. 6 illustrates another processor system.

DETAILED DESCRIPTION

[0012] As shown in FIG. 1, a processor 10 is connected to a memorycontroller hub 20. The processor may be a Pentium II class processor,other general purpose processor, or dedicated controller. The processormay be part of a work station, desktop personal computer, portablecomputer, or telecommunications, video, or graphics device. Memorycontroller hub 20 is connected to, and controls, main memory 30. Memorycontroller hub 20 also handles graphics traffic and traffic to and fromthe I/O controller hub. Main memory 30 can be, for example, a. RAMBUSmemory system including multiple memory modules, each holding RDRAMmemory chips. The individual modules can be of a comparable size tostandard dual inline memory modules.

[0013] The memory controller hub 20 interacts with main memory 30 usinga packetized protocol. The memory controller acts as an interpreterbetween the RAM bus and processor 10 so that the processor does not needto concern itself with the details of the RAM structure or operation.Other high speed RAM technologies using a memory controller to accessmain memory may be used as well.

[0014] Memory controller hub 20 and main memory 30 are clocked by memoryclock 40. For example, main memory may be differentially clocked at 400MHZ using dual phase clocking to provide an effective clock rate of 800MHZ. The processor is clocked by processor clock 50. Also coupled toprocessor 10 via I/O controller hub 55 is nonvolatile memory 60. Thenonvolatile memory 60 may be ROM, EPROM, EEPROM, battery-backed RAM, andthe like. The nonvolatile memory 60 stores the BIOS (basic input/outputsoftware) and may include SMM (system management mode software). The SMMmay also reside in the main memory.

[0015] The nonvolatile memory 60 stores the initialization software 70used to initialize memory controller hub 20. Initialization software 70may be part of the BIOS or part of the SMM software, if present. In someapplications, the initialization software may be independent of theBIOS, for example, in systems that do not have BIOS software external toprocessor 10. Memory controller hub 20 includes internal registers 90that control the address space mapping (“PAM registers”). Theseregisters control whether the address generator looks to nonvolatilememory 60 for instructions and data or looks to main memory 30.Alternately, the PAM registers may reside in I/O controller hub 55 or ina separate well in the processor such that power is not lost whenprocessor 10 is powered down. Connected to processor 10 is display orgraphics controller 95.

[0016] Processor 10 may include cache 110 to speed up memory accesstime. The cache may be internal to the processor chip or package and mayalso be external. I/O controller 55 contains a wake trigger statemachine 100 to process wake event triggers received from outside theprocessor. State machine 100 can also reside in memory controller hub 20or processor 10. This state machine enables the processor to respond towake events at a time before any software begins to execute.

[0017] Once the system is running, the system is in an awake state,memory controller hub 20 is initialized, portions of operating system 80are loaded into main memory 30, and the system is in normal operation.

[0018] Referring to FIG. 2, the operating system may determine thatpower should be conserved and that the system should enter a sleepstate. This determination may be triggered based on an innumerable hostof factors, such as a system idle time out, a request from a user, arequest from a hardware device, such as a low battery or hightemperature indication, or a request from an applications program.

[0019] Before entering a sleep state, in step 200 the operating systemprepares for the transition. This preparation may include housekeepingtasks, cache flushing, context saving, and the like. The operatingsystem may also determine which devices are to be placed in a “sleep”state. In circumstances where a system is designed to maximize powersavings, the entire system may be placed in a sleep state. In moresimple designs, only the processor and the memory subsystem may beplaced in a sleep state, while peripherals are left either fully poweredor turned off. The operating system also selects the desired sleep stateand sets the appropriate bit or bits in a sleep state register. Forexample, the ACPI specification includes the S1 and S2 sleep states thatprovide for a low latency return to the awake state.

[0020] In step 210, the processor transitions to the sleep state. Oneway to accomplish this transition is to set the appropriate bits in asleep enable register. Either a software or hardware process thendetects that this bit is set and asserts a sleep signal to theappropriate components. Processor clock 50 is powered down. Poweringdown may be accomplished by disconnecting power from the device itself,or may be accomplished by electrically disconnecting the incoming signalfrom the internal distribution lines internal to each chip. For example,processor clock 50 may be left running, but the processor mayelectrically disconnect the incoming clock signal so the processor'sinternal components are not being clocked. Likewise, individual devicesmay be powered down with circuitry internal to the devices that preventthe flow of power to some or all of the components inside the device. Inan RDRAM system, memory controller hub 20, main memory 30, and memoryclock 40 are powered down. When the main memory is power down, itscontents are not lost, but the main memory devices transition to a powerdown state that consumes very little power. An internal self refreshmechanism within main memory 20 keeps the memory contents when mainmemory is powered down. Also, memory clock 40 transitions to a low powerstate. In the low power state, physical power may or may not be removed.

[0021] In step 220, a wake event trigger is detected. This triggersignals that processor 10 should resume normal operation. In someapplications, this may be a return to full speed, full power mode. Inother applications, the system may awaken to a more drowsy state whereprocessor 10 may not be running at full speed. The wake event triggermay be generated by a source outside the system itself, such as a userpressing a “power on” or “resume” key, an incoming call signal from amodem or other telephony receiver, or it may be generated by a timertied to a particular time of day or some other event such as scheduledsystem maintenance.

[0022] In response to the detected wake event trigger, the systeminitializes the memory controller in step 230. In an RDRAM system thisincludes initializing the RAC and the RDRAM core. Other functionsperformed during initialization may be recalibration of the RAM busdrivers, synchronization of the RAM bus clock, and a general reset ofthe memory controller. This initialization is not performed exclusivelyby the hardware, but rather involves executing initialization software70 from nonvolatile memory 60.

[0023] After memory controller hub 20 is initialized, control is passedin step 240 from the initialization software 70 to operating system 80stored in main memory 30. Operating system 80 now processes the wakeevent trigger. This processing can include restoring the processorcontext, performing a quick system diagnostic, or other routinetypically executed following a wake event.

[0024]FIG. 3 shows an embodiment implementing the S1 sleep state withRDRAM. In normal operation, setting the sleep enable bit will cause theprocessor to transition to the S1 sleep state. In this embodiment,however, the system management mode software is used to mediate betweenthe sleep state and the RDRAM. A portion of the system management modesoftware is stored in nonvolatile memory 60 that also stores the BIOS(the BIOS storage device). The system management mode software, however,is inaccessible to the operating system. The operating system has nomeans by which it can directly jump to routines within the systemmanagement mode software.

[0025] To allow for control to efficiently and cleanly shift from theoperating system to the system management mode software, the processoris configured to respond to a sleep trigger with a system managementinterrupt (SMI). To accomplish this, the operating system writes a bitto a register in step 300. This register tells the hardware to generatean SMI in response to a sleep enable signal, rather than responding witha transition to a sleep state. In response to the SMI, the processordirects control to the system management mode software. In step 310, theSMI Handler, which services the SMI, flushes the cache. This cache flushavoids unified write backs in the L2 cache on instruction fetches. Ifthis step is performed, there will be no further memory writes until theprocessor transition from the sleep state. Next, as shown in step 320,the SMI Handler sets the PAM registers to point to the BIOS storagedevice. The PAM holds the address space mapping for the system. Once thePAM registers are pointing to the BIOS storage device, instructions anddata will be fetched from that device and not from the RDRAM. In step330, the SMI Handler executes a jump/branch instruction that points toan entry in the BIOS storage device.

[0026] In step 340, the SMI Handler clears the bit that causes theprocessor to generate an SMI in response to a sleep enable. Theprocessor is now reconfigured to enter a sleep state in response to asleep enable signal. In step 350, the sleep enable bit is set for asecond time. This time, however, it is the SMI Handler that sets thebit, not the operating system. The SMI Handler also identifies thedesired sleep mode. In this embodiment the desired sleep mode is the S1state. The processor detects that the sleep enable bit is set and, instep 360, the system transitions to the S1 sleep state. The processorclock and RDRAM clock are powered down. In this embodiment, theprocessor and RDRAM subsystem each have their own respective clocks. Inother embodiments the processor and memory subsystem can use the sameclock as their respective clocks. Once the RDRAM subsystem is powereddown, it requires reinitialization.

[0027] In step 370, a wake event trigger is received by the hardwaresignaling that the system should return to the awake state from thesleep state. The clocks are returned to their power on state. Theprocessor resumes instruction fetching. In step 380, the firstinstruction to be fetched is the instruction from the SMI Handlerfollowing the transition to the S1 state. In step 385, the SMI Handlerthen executes the instructions to initialize the RDRAM. In step 390, theSMI Handler then sets the PAM registers to point to an entry in theRDRAM. The SMI Handler then executes the return instruction and controltransfers to the operating system. In step 395, the operating systemexecutes the next instruction following the instruction in which it setthe sleep enable bit. The system has returned successfully from thesleep state and normal operation continues.

[0028]FIG. 4 shows an embodiment using the S2 state. The operatingsystem desires to enter the sleep state in step 410 and stores theresume address used by the BIOS in the RDRAM. The operating systemflushes the cache in Step 420, identifies the sleep state by writing theS2 state into the sleep type register, and enables the sleep state bywriting the appropriate information into the sleep enable register. Theprocessor and RDRAM clocks are powered down in step 430. In the S2state, the power to processor 10 is actually removed so that processor10 is not consuming either active or leakage power.

[0029] The system is in the S2 state in step 440. A wake event triggeris detected in step 450. Power is restored to the clocks. A processorreset (CPURST#) is also asserted resetting the processor. The systemcomes out of reset in step 460 and starts executing software at locationFFFFFFF0h. The PAM registers are configured to point to the BIOS storagedevice and not to shadow this space in the RDRAM. Alternatively, ahardware state machine can respond to the-wake event by changing the PAMregisters to point to the BIOS storage device. In step 470, the BIOSinitializes the RDRAM. In step 480, the BIOS redirects the PAM registersto execute software from the RDRAM. BIOS passes control to the operatingsystem via the resume address stored in RDRAM in step 410. In step 490,the operating system processes the wake event interrupt. In step 495,recovery from the sleep state is complete and normal operation in theawake state resumes.

[0030]FIG. 5 shows a processor and memory subsystem within the contextof a larger system, such as might be found in a desktop system, portablecomputer, portable communications device, set top box, or video andgraphics controller. Processor 510 and memory controller 520 areincorporated within the same chip. The processor interacts with thememory 530, preferably RDRAM, via memory controller 520 through memorybus 535. Memory controller 520 wakes and is initialized by the executionof software from BIOS storage device 540. It may be desirable in someapplications to incorporate the BIOS storage device into the same chipas processor 510 and memory controller 520.

[0031] Power to the system is supplied by power source 545. In aportable system, power source 545 may be a battery. In desk top or settop devices, the power source may be a DC source drawing AC line power.The power is distributed by power control circuitry 550. Power controlcircuitry is responsive to the processor to decrease or cut off power tovarious parts of the system. Power control circuitry 550 can also informprocessor 510 of a low power condition. As shown the power controlcircuitry interfaces with the processor in a manner independent of mainbus 560. In other embodiments, the power control circuitry may betreated as any other peripheral connected to the main bus. In a desk topsystem, the main bus may be a PCI bus. Connected to the main bus aredisplay 580, high density storage 590, and peripherals 590. In somesystems that are graphics intensive, display or graphics controller 580may have its own dedicated or high speed path to the processor. Displayor graphics controller 580 may be connected to processor 10 or memorycontroller hub 20 through a separate bus or may be integrated with thememory controller in the processor core. High density storage 590 willtypically be a hard drive. Peripherals 590 will vary with the particularapplication.

[0032] Referring to FIG. 6, three different configurations for a corechipset are shown. Configuration 1 has the processor 610 (CPU), graphicscontroller 620 (GFX), and memory controller 630 (also called a memorycontroller hub or MCH) integrated into a single chip 640. The I/Ocontroller hub 650 (ICH) and video controller hub 655 (VCH) are shown asdistinct chips. The VCH may also be incorporated into chip 640. ICH 650controls the operation of the main bus, for example, the main bus 560shown in FIG. 5. ICH 650 has an output (NRST) that resets chip 640. ICH650 has a separate output (PCIRST#) that resets the main bus, forexample, a PCI bus. In configuration 2, processor 610, GFX 620, and MCH630 are each in separate chips. In configuration 3, processor 610 is inits own chip. GFX 620 and MCH 630 are in a single chip. Inconfigurations 2 and 3, CPU 610 has its own reset input under control ofICH 650.

[0033] In configuration 1 chip 640 and all its components are powereddown in the sleep state, for example, an S2 state. In configuration 2,CPU 610 and MCH 630 are powered down. GFX 620 is left powered tomaintain a display. Alternatively, GFX 620 may be powered down toconserve even more power. In configuration 3, CPU 610, GFX 620, and MCH630 are powered down. Powering down the components in addition tostopping the clocks substantially reduces leakage currents.Additionally, the interface between ICH 650 and the other components isisolated. This interface is not a PCI interface, but a messagingprotocol based interface. In each configuration, the ICH is leftpowered. The ICH has hardware necessary to recover from the sleep state.Reducing or eliminating leakage power in the S2 state from CPU 610, GFX620, and MCH 630 will extend battery life in a substantial way in 0.18micron process technologies and beyond.

[0034] The disclosed embodiments are exemplary only. Other embodimentsare within the scope of the following claims.

Appendix

[0035] The S1 and S2 sleep states of the ACPI Specification, Revision1.0b, released Feb. 2, 1999:

[0036] 9.1.1 S1 Sleeping State

[0037] The S1 state is defined as a low wakeup latency sleeping state.In this state no system context is lost (CPU or chip set), and thehardware is responsible for maintaining all system context, whichincludes the context of the CPU, caches, memory, and all chipset I/O.Examples of S1 sleeping state implementation alternatives follow.

[0038] 9.1.1.1 S1 Sleeping State Implementation (Example 1)

[0039] This example references an IA processor that supports the stopgrant state through the assertion of the STPCLK# signal. When SLP_TYPxis programmed to the S1 value (the OEM chooses a value, which is thenplaced in the \_S1 object) and the SLP_ENx bit is subsequently set, thehardware can implement an S1 state by asserting the STPCLK# signal tothe processor, causing it to enter the stop grant state. In this case,the system clocks (PCI and CPU) are still running. Any enabled wakeupevent should cause the hardware to de-assert the STPCLK# signal to theprocessor.

[0040] 9.1.1.2 S1 Sleeping State Implementation (Example 2)

[0041] When SLP_TYPx is programmed to the S1 value and the SLP_ENx bitis subsequently set, the hardware will implement an S1 state by doingthe following:

[0042] 1. Place the processor into the stop grant state.

[0043] 2. Stop the processor's input clock, placing the processor intothe stop clock state.

[0044] 3. Places system memory into a self-refresh or suspend-refreshstate. Refresh is maintained by the memory itself or through some otherreference clock that is not stopped during the sleeping state.

[0045] 4. Stop all system clocks (asserts the standby signal to thesystem PLL chip). Normally the RTC will continue running.

[0046] In this case, all clocks in the system have been stopped (exceptfor the RTC's clock). Hardware must reverse the process (restartingsystem clocks) upon any enabled wakeup event.

[0047] 9.1.2 S2 Sleeping State

[0048] The S2 state is defined as a low wakeup latency sleep state. Thisstate is similar to the S1 sleeping state, except that the CPU andsystem cache context is lost (the OS is responsible for maintaining thecaches and CPU context). Additionally, control starts from theprocessor's reset vector after the wakeup event. Before setting theSLP_EN bit, the ACPI driver will flush the system caches. If theplatform supports the WBINVD instruction (as indicated by the WBINVD andWBINVD_FLUSH flags in the FACP table), the OS will execute the WBINVDinstruction. If the platform does not support the WBINVD instruction toflush the caches, then the ACPI driver will attempt to manually flushthe caches using the FLUSH_SIZE and FLUSH_STRIDE fields in the FACPtable. The hardware is responsible for maintaining chipset and memorycontext. An example of a S2 sleeping state implementation follows.

[0049] 9.1.2.1 S2 Sleeping State Implementation Example

[0050] When SLP-TYPx is programmed to the S2 value (found in the \_S2object) and then the SLP_EN bit is set, the hardware will implement anS2 state by doing the following:

[0051] Stop system clocks (the only running clock is the RTC).

[0052] Place system memory into a self or suspend refresh state.

[0053] Power off the CPU and cache subsystem.

[0054] In this case, the CPU is reset upon detection of the wakeupevent; however, core logic and memory maintain their context. Executioncontrol starts from the CPU's boot vector. The BIOS is required to:

[0055] Program the initial boot configuration of the CPU (such as theCPU's MSR and MTRR registers).

[0056] Initialize the cache controller to its initial boot size andconfiguration.

[0057] Enable the memory controller to accept memory accesses.

[0058] Call the waking vector.

What is claimed is:
 1. In a system comprising a processor, a firstmemory, a first memory controller, and a second memory, a method fortransitioning between an awake state and a sleep state comprising:detecting a trigger to transition from the sleep state to the awakestate; initializing the first memory controller in response to thedetecting, the initializing comprising executing software in the secondmemory; and executing software in the first memory after theinitializing.
 2. The method of claim 1 further comprising: preparing,under control of software stored in the first memory, for a transitionfrom the awake state to the sleep state; and transitioning to the sleepstate.
 3. The method of claim 2 wherein the software stored in the firstmemory comprises operating system software.
 4. The method of claim 2wherein the first memory comprises RDRAM.
 5. The method of claim 4wherein the first memory controller resides in the same chip as theprocessor.
 6. The method of claim 5 wherein the software in the secondmemory comprises BIOS software.
 7. The method of claim 5 wherein thesoftware in the second memory comprises software inaccessible by theoperating system.
 8. The method of claim 5 wherein the software in thesecond memory comprises system management mode software.
 9. The methodof claim 1 wherein the processor and memory controller have inputs forreceiving respective clock signals, the method further comprisingpreventing the receiving of the respective clock signals prior to thedetecting.
 10. The method of claim 2 wherein the preparing comprises:configuring the processor to execute the software stored in the secondmemory in response to a sleep trigger signal from the operating system;receiving a first sleep trigger signal from the operating system;executing the software stored in the second memory in response to thereceiving; reconfiguring the processor to transition to the sleep statein response to a sleep trigger signal; and receiving a second sleeptrigger signal.
 11. The method of claim 10 wherein the software storedin the second memory comprises system management mode software, themethod further comprising generating a system management interrupt inresponse to the receiving of the first sleep trigger.
 12. The method ofclaim 10 wherein the initializing executes the software stored in thesecond memory at the instruction following the last instruction executedbefore transitioning to the sleep state.
 13. The method of claim 2wherein the transitioning transitions the processor into an S1 state.14. The method of claim 2 wherein the transitioning transitions theprocessor into an S2 state.
 15. The method of claim 2 wherein thepreparing comprises flushing a cache.
 16. The method of claim 2 furthercomprising resetting the processor prior to the initializing.
 17. In asystem comprising a processor, a first memory, a first memorycontroller, and a second memory, wherein the processor and memorycontroller have inputs for receiving respective clock signals, and thefirst memory stores operating system software, a method fortransitioning between an awake state and a sleep state comprising:preparing, under control of the operating system software, for atransition from the awake state to the sleep state, the preparingincluding configuring the address space mapping to point to the secondmemory following the detecting; preventing the receiving of therespective clock signals; transitioning to the sleep state; detecting atrigger to transition from the sleep state to the awake state;initializing the first memory controller in response to the detecting,the initializing comprising executing BIOS software in the secondmemory; executing operating system software after the initializing. 18.The method of claim 17 further comprising: storing a BIOS resume addressin the first memory; and transferring control from the BIOS to theoperating system following the initializing using the resume addressstored in the first memory.
 19. The method of claim 18 furthercomprising powering down the first memory controller prior to thedetecting.
 20. A system comprising: a processor having an awake stateand a sleep state; a first memory; a first memory controller; a secondmemory; and software stored in the second memory that executes toinitialize the first memory controller responsive to a trigger signalsignaling a transition from the sleep state to the awake state.
 21. Thesystem of claim 20 wherein: the first memory stores operating systemsoftware; the second memory is nonvolatile memory; the second memorystores BIOS software; and the operating system software is configured tocontrol a transition from the awake state to the sleep state.
 22. Thesystem of claim 21 wherein: the operating system stores a BIOS resumeaddress in the first memory prior to a transition from the awake stateto the sleep state; and the BIOS software returns control to theoperating system using the stored BIOS resume address after the memorycontroller is initialized.
 23. The system of claim 21 wherein the firstmemory comprises RDRAM.
 24. The system of claim 21 wherein the secondmemory comprises RAM.
 25. The system of claim 21 further comprisingsystem management mode software, the system management mode softwarebeing inaccessible by the operating system, and wherein the systemmanagement mode software initializes the first memory.
 26. The system ofclaim 20 wherein the processor, first memory, and first memorycontroller have clock inputs, the system comprising clock disablecircuitry preventing the internal clocking of the processor, firstmemory, and first memory controller.
 27. The system of claim 20 whereinthe processor and first memory controller reside within a common chip.28. The system of claim 20 further comprising cache residing in the samechip as the processor and first memory controller and wherein theoperating system is configured to flush the cache prior to thetransition from the awake state to the sleep state.
 29. A portablecomputer system comprising: a power storage medium; a display; aprocessor; a processor clock; a first memory; a first memory controller;a second memory; wherein the system includes an awake state and a sleepstate; wherein the processor and first memory controller are not clockedin the sleep state; and wherein software in the second memoryinitializes the first memory controller responsive to a transition fromthe sleep state to the awake state.
 30. The system of claim 29 furthercomprising circuitry to disable the flow of power internal to theprocessor, first memory controller, and first memory.